this datasheet contains new product informa tion. anachip corp. reserves the rights to modify the product sp ecification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rev. 1.0 dec 16, 2004 1/10 features peel? 22lv10az -25 cmos programmable electrically erasable logic device low voltage, ultra low power operation - vcc = 2.7 to 3.6 v - icc = 5 a (typical) at standby - icc = 1.5 ma (typical) at 1 mhz - meets jedec lv interface spec (jesd8-a) - 5 volt tolerant inputs and i/o?s cmos electrically erasable te c hn o l o gy - superior factory testing - reprogrammable in plastic package - reduces retrofit and development costs application versatility - replaces random logic - super set of standard plds - pin and jedec compatible with 22v10 - ideal for battery powered systems - replaces expensive oscillators general description the peel?22lv10az is a programmable electrically erasable logic (peel?) spld (simple programmable logic device) that operates over the supply voltage range of 2.7v-3.6v and fea- tures ultra-low, automatic ?zero? power-down operation. the peel?22lv10az is logically and functionally similar to ana- chip?s 5v peel?22cv10a+ and peel?22cv10az. the ?zero power? (50 a max. icc) power-down mode makes the peel?22lv10az ideal for a broad range of battery-powered portable equipment applications, from hand-held meters to pcm- cia modems. ee-reprogrammability provides both the conve- nience of fast reprogramming for product development and quick product personalization in manufacturing, including engineering change orders. figure 26 pin configuration architectural flexibility - enhanced architecture fits in more logic 3 - 133 product terms x 44 input and array - 12 inputs and 10 i/o pins - 12 possible macrocell configurations - asynchronous clear, synchronous preset - independent output enables - programmable clock; pin 1 or p-term - programmable clock polarity - 24 pin dip/soic/tssop and 28 pin plcc - schmitt triggers on clock and data inputs schmitt trigger inputs - eliminates external schmitt trigger devices - ideal for encoder designs the differences between the peel?22lv10az and peel?22cv10a include the addition of programmable clock polarity, p-term clock, and schmitt trigger input buffers on all inputs, including the clock. schmitt trigger inputs allow direct input of slow signals such as biomedical and sine waves or clocks. like the peel?22cv10, the peel?22lv10az is a pin and jedec compatible, logical superset of the industry stan- dard pal22v10 spld (figure 26). the peel?22lv10az pro- vides additional architectural features that allow more logic to be incorporated into the design. the peel?22lv10az architec- ture allows it to replace over twenty standard 24-pin dip, soic, tssop and plcc packages. figure 26 block diagram i/clk 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 i 10 i 11 gnd 12 24 vcc 23 i/o 22 i/o 21 i/o 20 i/o ? 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i dip tss op plcc so ic not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 2/10 not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 3/10 function description the peel?22lv10az implements logic functions as sum-of- products expressions in a programmable-and/fixed-or logic array. user-defined functions are created by programming the connections of input signals into the array. user-configurable output structures in the form of i/o macrocells further increase logic flexibility. architecture overview the peel?22lv10az architecture is illustrated in the block diagram of figure 26. twelve dedicated inputs and 10 i/os pro- vide up to 22 inputs and 10 outputs for creation of logic func- tions. at the core of the device is a programmable electrically- erasable and array that drives a fixed or array. with this struc- ture, the peel?22lv10az can implement up to 10 sum-of- products logic expressions. associated with each of the ten or functions is an i/o macrocell that can be independently programmed to one of 12 different configurations, including the four standard 22v10 modes. the programmable macrocells allow each i/o to be used to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the and array. and/or logic array the programmable and array of the peel?22lv10az (shown in figure 3) is formed by input lines intersecting product terms. the input lines and product terms are used as follows: 44 input lines: ? 24 input lines carry the true and complement of the signals applied to the 12 input pins ? 20 additional lines carry the true and complement values of feedback or input signals from the 10 i/os 133 product terms: ? 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) are used to form sum of product functions ? 10 output enable terms (one for each i/o) ? 1 global synchronous preset term ? 1 global asynchronous clear term ? 1 programmable clock term at each input-line/product-term intersection, there is an eeprom memory cell that determines whether or not there is a logical connection at that intersection. each product term is essentially a 44-input and gate. a product term that is con- nected to both the true and complement of an input signal will always be false and thus will not affect the or function that it drives. when all the connections on a product term are opened, a ?don?t care? state exists and that term will always be true. when programming the peel?22lv10az, the device pro- grammer first performs a bulk erase to remove the previous pat- tern. the erase cycle opens every logical connection in the array. the device is configured to perform the user-defined function by programming selected connections in the and array. (note that peel? device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function). programmable i/o macrocell the unique twelve-configuration output macrocell provides com- 3 plete control over the architecture of each output. the ability to configure each output independently lets you to tailor the config- uration of the peel?22lv10az to the precise requirements of your design. macrocell architecture each i/o macrocell, as shown in figure 27, consists of a d-type flip-flop and two signal-select multiplexers. the configuration of each macrocell is determined by the four eeprom bits control- ling these multiplexers. these bits determine output polarity, out- put type (registered or non-registered) and input-feedback path (bidirectional i/o, combinatorial feedback). refer to table 1 for details. equivalent circuits for the twelve macrocell configurations are illustrated in figure 1. in addition to emulating the four pal-type output structures (configurations 3, 4, 9, and 10), the macrocell provides eight additional configurations. when creating a peel? device design, the desired macrocell configuration is generally specified explicitly in the design file. when the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the jedec programming file. output type the signal from the or array can be fed directly to the output pin (combinatorial function) or latched in the d-type flip-flop (regis- tered function). the d-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. when the synchronous preset term is satisfied, the q out- put of the register is set high at the next rising edge of the clock input. satisfying the asynchronous clear sets q low, regardless of the clock state. if both terms are satisfied simultaneously, the clear will override the preset. output polarity each macrocell can be configured to implement active-high or active-low logic. programmable polarity eliminates the need for external inverters. output enable the output of each i/o macrocell can be enabled or disabled under the control of its associated programmable output enable product term. when the logical conditions progra mmed on the output enable term are satisfied, the output signal is propagated to the i/o pin. otherwise, the output buffer is switched into the high-impedance state. under the control of the output enable term, the i/o pin can func- tion as a dedicated input, a dedicated output, or a bi-directional i/ o. opening every connection on the output enable term will per- manently enable the output buffer and yield a dedicated output. conversely, if every connection is intact, the enable term will not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 4/10 always be logically false and the i/o will function as a dedicated input. input/feedback select the peel?22lv10az macrocell also provides control over the feedback path. the input/feedback signal associated with each i/ o macrocell can be obtained from three different locations; from the i/o input pin, from the q output of the flip-flop (registered feedback), or directly from the or gate (combinatorial feed- back). bi-directional i/o the input/feedback signal is taken from the i/o pin when using the pin as a dedicated input or as a bi-directional i/o. (note that it is possible to create a registered output function with a bi-direc- tional i/o, refer to figure 27). combinatorial feedback the signal-select multiplexer gives the macrocell the ability to feedback the output of the or gate, bypassing the output buffer, regardless of whether the output function is registered or combi- natorial. this feature allows the creation of asynchronous latches, even when the output must be disabled. (refer to configurations 5, 6, 7, and 8 in figure 1.) registered feedback feedback also can be taken from the register, regardless of whether the output function is programmed to be combinatorial or registered. when implementing a combinatorial output func- tion, registered feedback allows for the internal latching of states without giving up the use of the external output. figure 27 block diagram of the peel?22lv10az i/o macrocell programmable clock options a unique feature of the peel?22lv10az is a programmable clock multiplexer that allows the user to select true or comple- ment forms of either input pin or product-term clock sources. operates in both 3 volt and 3.3 volt systems the peel?22lv10az is designed to operate with a v cc range of 2.7 to 3.6 volts d.c. this allows operation in both 3 vo l t 10% (battery operated) and 3.3 volt 10% (power supply oper- ated) systems. the propagation delay t pd is 5 ns slower at the lower voltage, but this is typically not an issue in battery-oper- ated systems (see ?a.c. electrical characteristics? on page 64). zero power feature the cmos peel?22lv10az features ?zero-power? standby operation for ultra-low power consumption. with the ?zero- power? feature, transition-detection circuitry monitors the inputs, i/os (including clk) and feedbacks. if these signals do not change for a period of time greater than approximately two t pd ?s, the outputs are latched in their current state and the device auto- matically powers down. when the next signal transition is detected, the device will ?wake up? for active operation until the signals stop switching long enough to trigger the next power- down. (note that the tpd is approximately 5 ns. slower on the first transition from sleep mode.) as a result of the ?zero-power? feature, significant power sav- ings can be realized for combinatorial or sequential operations when the inputs or clock change at a modest rate. see figure 28. when the peel?22lv10az is powered up, a built-in feature holds the outputs in tri-state until vcc reaches 2.2v. this pre- vents output transitions during power-up. figure 28 typical icc vs. input clock frequency for the 22lv10az 100 10 icc 1 in ma 0.1 ac = asynchronous clear sp = synchronous preset 0.01 0.01 0.1 1 10 100 frequency in mhz not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 5/10 figure 1 equivalent circuits for the twelve configurations of the peel?22lv10az+ i/o macrocell not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 6/10 schmitt trigger inputs the peel?22lv10az has schmitt trigger input buffers on all inputs, including the clock. schmitt trigger inputs allow direct input of slow signals such as biomedical and sine waves or clocks. they are also useful in cleaning up noisy signals. this makes the peel?22lv10az especially desirable in portable applications where the environment is less predictable. design security the peel?22lv10az provides a special eeprom security bit that prevents unauthorized reading or copying of designs pro- grammed into the device. the security bit is set by the pld pro- grammer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. once the security bit is set it is impossible to verify (read) or program the peel? until the entire device has first been erased with the bulk-erase function. signature word the signature word feature allows a 64-bit code to be pro- grammed into the peel?22lv10az if the peel?22lv10az+ software option is used. the code can be read back even after the security bit has been set. the signature word can be used to iden- tify the pattern programmed into the device or to record the design revision, etc. programming support anachip?s jedec file translator allows easy conversion of exist- ing 24 pin pld designs to the peel?22lv10az, without the need for redesign. anachip also offers (for free) its proprietary winplace software, an easy-to-use entry level pc-based soft- ware development system. programming support includes all the popular third party pro- grammers such as bp microsystems, system general, logical devices, and numerous others. not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 7/10 absolute maximum ratings this device has been designed and tested for the specified operat- ing ranges. improper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may cause permanent damage. 3 operating range d.c. electrical characteristics over the operating range (unless otherwise specified) symbol parameter conditions min max unit v oh output high voltage - ttl v cc =min, i oh =-2.0ma v cc -0.5 v v ohc output high voltage - cmos v cc =min, i oh =-10 a v cc -0.3 v v ol output low voltage - ttl v cc =min, i ol =8.0ma 0.4 v v olc output low voltage - cmos v cc =min, i ol =10 a 0.15 v v ih input high level v cc =3.3v 2.0 5.5 v v il input low level v cc =3.3v -0.3 0.8 v v h input voltage hysteresis 0.2 v v cc =max, gnd v in v cc , i/o=high z 10 a i in input and i/o leakage current v cc =max, gnd v in 5.5v, i/o=high z 1 ma i sc 10 output short circuit current v cc =max, v o =0.5v, ta=25 o c -30 -135 ma i ccs v cc current, standby v in =0v or v cc , all outputs disabled 5 5(typ) 25 a i cc 11 v cc current, f=1mhz v in =0v or v cc , all outputs disabled 5 1.5(typ) 3 ma c in 8 input capacitance 6 pf c out 8 output capacitance t a =25 o c, v cc =max @f=1mhz 12 pf not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 8/10 a.c. electrical characteristics over the operating range 9 switching waveforms inputs, i/o, registered feedback, synchronous preset clock notes: asynchronous reset registered outputs combinatorial outputs 1. minimum dc input is -0.5v, however, inputs may undershoot to -2.0v for peri- ods less than 20 ns. 2. v i and v o are not specified for program/verify operation. 3. the supply vo l t a g e range of 2.7 to 3.6v was chosen to allow this part to be used in both 3v 10% and 3.3v 10% applications. 4. test points for clock and vcc in t r and t f are referenced at the 10% and 90% levels. 5. i/o pins are 0v and v cc . 6. ?input? refers to an input pin signal. 7. t oe is measured from input transition to v ref 0.1v, t od is measured from input transition to v oh -0.1v or v ol +0.1v; v ref =v l. 8. capacitances are tested on a sample basis. 9. test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 10. test one output at a time for a duration of less than 1 second. 11. i cc for a typical application: this parameter is tested with the device pro- grammed as a 10-bit counter. 12. parameters are not 100% tested. specifications are based on initial character- ization and are tested after any design process modification that might affect oper- ational frequency. 13. t pd , t oe , t od , t co , t sc , and t ap are approximately 5 ns. slower on the first transaction from sleep mode. 14. input at gnd. not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 9/10 peel? device and array test loads ordering information part number speed temperature package peel22lv10azp-25 (l) 25ns commercial 24-pin plastic dip PEEL22LV10AZJ-25 (l) 25ns commercial 28-pin plcc peel22lv10azs-25 (l) 25ns commercial 24-pin soic peel22lv10azt-25 (l) 25ns commercial 24-pin tssop part number peel tm 22lv10az p-25x package p = 24-pin plastic 300 mil dip s = 24-pin soic 300 mil gullwing speed lead free blank : normal l : lead free package j = 28-pin plastic (j) leaded chip carrier (plcc) suffix device t = 24-pin tssop 170 mil -25 = 25ns tpd not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 10/10 anachip corp. head office, 2f, no. 24-2, industry e. rd. iv, science-based industrial park, hsinchu, 300, taiwan tel: +886-3-5678234 fax: +886-3-5678368 anachip usa 780 montague expressway, #201 san jose, ca 95131 tel: (408) 321-9600 fax: (408) 321-9696 email: sales_usa@anachip.com website: http://www.anachip.com ?2004 anachip corp. anachip reserves the right to make changes in specifications at any time and without notice. the information furnished by anachip in this publi cation is believed to be accurate and reliable. however, there is no responsibility assumed by an achip for its use nor for any infringements of patents or other rights of third parties resulting from its use. no license is granted under any patents or patent rights of anachip. anachip?s pr oducts are not authorized for use as critical components in life support devices or systems. marks bearing ? or ? are registered trademarks and trademarks of anachip corp. not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
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